FIGS. 1 and 2 depict a small portion of a conventional magnetic random access memory (magnetic RAM) 1 that utilizes spin transfer based switching. The conventional magnetic RAM 1 includes a conventional magnetic storage cell 10 including a magnetic element 12 and a selection device 14. The selection device 14 is typically a transistor, such as a CMOS transistor, and has a gate 15. Also depicted are a word line 16, a bit line 18, and source line 20. The word line 16 is typically oriented perpendicular to the bit line 18. The source line 20 is typically either parallel or perpendicular to the bit line 18, depending on specific architecture used for the magnetic RAM 1.
The conventional magnetic element 12 is configured to be changeable between high and low resistance states by driving a current through the conventional magnetic element 12. The current is spin polarized when passing through the magnetic element 12 and changes the state of the magnetic element 12 by the spin transfer effect. For example, the magnetic element 12 may be a magnetic tunnel junction (MTJ) configured to be written using the spin transfer effect. Typically, this is achieved by ensuring that the magnetic element 12 has, for example, a sufficiently small cross-sectional area as well as other features desirable for switching using the spin transfer effect. When the current density is sufficiently large, the current carriers driven through the magnetic element 12 may impart sufficient torque to change the state of the magnetic element 12. When the write current is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current is driven in the opposite direction, the state may be changed from a high resistance state to a low resistance state.
FIG. 1 depicts the conventional magnetic storage cell 10 being written to a first state by the write current, IW1, being driven in a first direction. Thus, in FIG. 1 the bit line 18 and the word line 16 are activated. The selection device 14 is turned on. The first write current is driven from the bit line 18 to the source line 20. Consequently, a high voltage, Vwrite, is coupled to the bit line 18 while the source line 20 is coupled to ground. The first write current thus flows through the magnetic element 12. FIG. 2 depicts the conventional magnetic element 10 being written to a second state by a second write current, IW2, being driven in the opposite direction. The bit line 18 and the word line 16 are still activated and the selection device 14 turned on. The high voltage, Vwrite, is coupled to the source line 20 while the bit line 18 is coupled to ground. Thus, the second write current, IW2, flows through the conventional magnetic element 12.
For a read operation, the bit line 18 and the word line 16 are activated. Consequently, the selection device 14 is turned on. A read current is driven through the magnetic element 12. The read current is typically less than either the first current IW1 or the second write current IW2.
The conventional magnetic RAM 1 utilizes a write current driven through the magnetic element 12 in order to program data to the conventional magnetic storage cell 10. Thus, the conventional magnetic RAM 1 uses a more localized phenomenon in programming the conventional magnetic element 12. Unlike a conventional MRAM that switches its state by applying magnetic fields, the conventional magnetic RAM 1 does not suffer from a half select write disturb problem. Moreover, for higher density memories, and smaller individual magnetic elements 12, a lower current corresponds to the same current density as a larger magnetic element. Thus, the current required to write to the conventional magnetic RAM 1 decreases with decreasing size, which is desirable. This trend is distinct from a conventional MRAM that switches its state by applying magnetic fields, which requires a significantly higher write current at lower sizes. For example, for a conventional magnetic element 12 having a size less than approximately two hundred nanometers, the conventional magnetic RAM 1 utilizes a lower write current than the write current used to generate a write field for a conventional MRAM that switches its state by applying magnetic fields.
Although the conventional magnetic RAM 1 generally utilizes a lower current and a more localized programming scheme, one of ordinary skill in the art will readily recognize that the use of the conventional magnetic RAM 1 in higher density memory applications may be limited by various factors. For example, the size of a conventional storage cell 10 may primarily be determined by the write current used to switch the conventional magnetic element 12. Advanced photolithography techniques typically result in a transistor having a gate 15 width of less than 0.2 to 0.3 microns. A typical transistor outputs approximately four hundred to five hundred micro-Amperes per micron of gate width. Consequently, the selection device 14 typically produces current of less than one hundred to one hundred fifty micro-Amperes. The conventional magnetic storage cell 10 may require two to ten times that current in order to switch the state of the conventional magnetic element 12. In order to support such a large current, the selection device 14 is made significantly larger than the 0.2-0.3 microns capable of being produced. Consequently, the size of the conventional storage cell 10 is increased.
The situation may be further complicated in an actual magnetic RAM 1, which typically includes numerous storage cells 10 in an array. In such an array, a large number of cells are typically connected in parallel to each bit line 18. For example, the conventional magnetic RAM may connect thousands of conventional storage cells 10 to each bit line and may include a large number of bit lines. During a single read or write operation, only a subset of the cells on a bit line 18 is activated. For example, a single storage cell 10 along a bit line 18 may be activated. The remaining cells (not shown) are presumed to be off. However, a typical selection device 14 has a small leakage current in the off state. A typical transistor has a drain-to-source current on/off ratio of approximately one thousand to one million. Consequently, one thousand cells 10 in the off state may collectively have a leakage current that is comparable to a transistor 14 in the on state for the single storage cell 10 that is on. This leakage current may, therefore, significantly reduce the current available for reading of and writing to the desired storage cell 10 and increase power consumption. Moreover, the critical dimension, f, of RAM decreases, the magnitude of the available supply voltage formed using conventional CMOS is decreased. Consequently, for smaller, denser memories, the problem of leakage current may be exacerbated.
One remedy for the leakage is to increase the threshold voltage of the selection device 14. However, such a remedy results in a in a lower available source-drain current. Furthermore, an increase in the threshold voltage is typically accomplished by making the conventional storage device 14 larger. As a result, the conventional storage cell 10 is again made larger, which is undesirable.
Moreover, when the conventional magnetic element 12 is coupled with a transistor, other issues arise. The drain-source current is typically smaller for the combination of the conventional magnetic element 12 and the transistor 14 than for the transistor 14 by itself. A voltage, for example a supply voltage, applied to the combination of the conventional magnetic element 12 and the transistor 14 is split between the conventional magnetic element 12 and the transistor 14. Stated differently, a portion of the voltage drop occurs across the transistor 14, while a remaining portion of the voltage drop occurs across the conventional magnetic element 12. As a result, a smaller voltage is available to provide a voltage drop across the transistor 14. The transistor drain-source current is thereby reduced.
Furthermore, the source-drain current may be asymmetric for the combination of the conventional magnetic element 12 and the transistor 14. The transistor source-drain current differs depending upon whether the conventional magnetic element 12 is connected to the drain side or to the source side of the transistor 14. This difference may range from ten to fifty percent. For example, application of a supply voltage to the bit line 18 and application of the same voltage to the source line 20 may result in different currents through the transistor 14. Thus, the source-drain current for a write current driven in one direction, as in FIG. 1, may be different than for a current driven in the opposite direction, as in FIG. 2. As a result, writing to the conventional magnetic element 10 may be asymmetric. Such an asymmetry is undesirable.
In addition, semiconductor memories have memory cells having areas in the range of 4 f2 to 12 f2, where f is the critical photolithographic dimension. It would be desirable to produce magnetic RAM having such size ranges in order to better compete with other types of nonvolatile storage. However, the above difficulties in the size of the conventional storage cell 10, the write currents required, the sizes of the selection devices 14, the problems due to leakage current, and issues with the connection between elements of a conventional storage cell 10 may make it difficult to use the magnetic RAM 1 using current for writing to the conventional magnetic element 12 as an alternative to other types of memory.
Accordingly, what is desired is a method and system for providing and utilizing memory cells that may employ spin transfer based switching, which utilize a smaller write current, which provide for a more symmetric write current, and may be suitable for a higher density magnetic memory. The present invention addresses such a need.